Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer science, or equivalent practical experience

• 3 years of experience with development projects in VLSI

• Experience in RTL design, verification (UVM, System Verilog), System-On-Chip design/integration flow, and design automation

Preferred qualifications:

• Master’s degree in Computer or Electrical Engineering

• Experience in designing or verifying digital logic using SystemVerilog for FPGAs, ASICs, and/or SoCs

• Experience in design verification technologies like UVM, simulation, coverage collection, test planning, debug, integration flows, build/release flows

• Experience in programming languages such as C++ and scripting languages such as Python/Perl/TCL

• Experience in interacting with Electronic Design Automation (EDA) vendors and understanding of some of the EDA design tools like VCS, Xcelium, Verdi, Spyglass, Coretools, Defacto/Magillem

• Excellent scripting skills in Python, Perl, and TCL

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

As a CAD Methodology Engineer, you will plan and execute work in an innovative and fast-paced environment, with a focus on providing cutting edge flow and methodology solutions for high performance IP development. You will work with architects, logic designers, and verification engineers to develop flows to build and verify complex IPs and subsystems.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

• Design new RTL and/or design verification methodologies and flows for high performance IPs.

• Identify inefficiencies and improvement opportunities in the front-end chip implementation process and propose ideas to address them.

• Be responsible to design our custom RTL and/or infrastructure solutions for IPs and hierarchical designs, and make it a delightful experience for our customers.

• Work with cross-functional teams and chip leads globally to drive changes.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.